
Prototype bring-up and 10 GbE debugging · published by Aaron on LinkedIn
Owl Cyber Defense · Three summer terms
FPGA verification with product-level ownership.
Contributed inside the verification stack for in-development cross-domain security hardware using SystemVerilog, UVM, formal verification methodologies, and Cadence Xcelium.
- 01 Built and exercised verification paths around management and GPIO behavior.
- 02 Worked across multiple clock domains, AXI4 flows, Ethernet MAC IP, and Spartan-7 hardware.
- 03 Used simulation and formal techniques to surface design issues before hardware integration.
- 04 Demonstrated an Ethernet-controlled RAM and LED flow in a company-wide presentation.
